Most commercial uses of power MOSFETs are as electronic "switches". As a switch, there are two key characteristics of a power MOSFET: its breakdown voltage and its on-resistance. Its breakdown voltage is a measure of the MOSFET's ability to withstand voltage when it is in an "off" or "open" condiction, and its on-resistance is a measure of its resistance when it is in an "on" or "closed" condition. To improve the operation of the device as a switch, the objective is to make the breakdown voltage as high as possible and the on-resistance as low as possible. A perfect device would have an infinite breakdown voltage and zero on-resistance.
Several categories of power MOSFETs exist. In vertical devices the current flows generally from contacts on the top surface of a semiconductor die to contacts on the opposite side. One variety of vertical device is the trench-gated MOSFET, wherein the gate is formed in trenches that extend downward from the top surface of the die, and the channel regions are located along the side walls of the trenches. Trenched-gated MOSFETs have several advantages, one of which is that the cell density can be made greater, and this in turn reduces the on-resistance of the device. Despite these advantages, many vertical devices continue to be fabricated with the gate located over the top surface of the die and the body and channel region being formed by two diffusions of opposite conductivity. For this reason, and since the flat top surface of the die remains intact, these are sometimes called vertical planar double-diffused MOSFETs, or vertical planar DMOSFETs.
FIGS. 1A-1C are cross-sectional views of the cells of three types of vertical planar DMOSFETs. Each of the MOSFETs is formed in an epitaxial (epi) layer 112 which is grown over an N+ substrate 110. Epi layer 112 is generally lightly doped with N-type atoms, but as indicated additional N-type atoms or P-type atoms are implanted into certain portions of epi layer 112.
In N-channel DMOSFET 100 shown in FIG. 1A, a polysilicon gate 120 is separated from epi layer 112 by an oxide (SiO.sub.2) layer 121. When MOSFET 100 is turned on, current flows vertically from the N+ substrate, which serves as the drain, laterally through a channel region 127 within the P-body 122 adjacent the top surface of epi layer 112, and to an N+ source region 123. The P-body 122 and N+ source region 123 are both self-aligned with the gate 120 and are formed by successive P- and N-type diffusions through the top surface of N-epi layer 112, the former of which is allowed to extend laterally under the gate 120. The P-body 122 and N+ source region 123 are shorted together by means of a metal layer 126 and a P+ body contact region 124. An optional deep P+ region 125 is used primarily to prevent any parasitic NPN bipolar action involving N+ source region 123, P-body 122 and N-type epi layer 112.
MOSFET 102 shown in FIG. 1B is similar to MOSFET 100, but gate 130 is fabricated in a terraced form over a thick oxide layer 132 to reduce the capacitance between gate 130 and epi layer 112 and thereby improve the switching speed of the device. Thick oxide layer 132 is typically formed by a LOCOS (local oxidation of silicon) process, although oxide etchback methods (where the oxide layer is grown, masked and etched) can also be used. The inclusion of the thick oxide layer 132 does not appreciably increase the lateral dimension of the MOSFET because the facing portions of P-body 122 must in any case be separated sufficiently to avoid undue current-crowding the in the central region of the MOSFET cell. This current crowding is not the same as minority carrier crowding in a bipolar junction transistor but is more like that of a pinch resistor in the sense that the majority carrier current must flow between the two P-body diffusions. With a reduced cross-sectional area for the current flow, the corresponding resistance in this region is higher than it would be if the opening (gate dimension) were larger.
MOSFET 104 shown in FIG. 10 is also similar to MOSFET 100, but a shallow N- region 134 is formed adjacent the surface of epi layer 112 between the portions of P-body 123, as described in U.S. Pat. No. 4,642,666 to Lidow et al. (although the corresponding region is designated as an N+ region in that patent). N- region is lightly doped but is still more heavily doped than N-epi layer 112 and thus lowers the resistance in the "neck" or "common conduction" region between the portions of P-body 122. N- region 134 is formed either by implanting N-type dopant from the sides and allowing it to diffuse laterally or by implanting it from the top. While this technique of reducing the on-resistance works quite well for 400-500 V devices it has relatively little impact for devices rated at 100 V or less. With devices rated at 100 V and less the N- region 134 must be doped so heavily to have any effect on resistance that it affects the breakdown of the device and furthermore moves the location of the breakdown towards the surface of the silicon below the gate. Note that the N- region 134 extends between the two facing portions of P-body 122. Breakdown in the location near the juxtaposed N- region 134 and P-body 122 can lead to impact ionization and hot carrier injection and consequent damage to the gate oxide layer.
FIG. 2A is a graph showing the normalized on-resistance R.sub.DS W of a vertical DMOSFET as a function of the gate surface dimension Y.sub.gate (see FIG. 1A). As Y.sub.gate is reduced down to about 3 or 4 .mu.m the increased cell density causes the on-resistance to decrease. Beyond about 3 or 4 .mu.m, however, current-crowding in the "JFET" region directly beneath the gate causes the on-resistance to increase rapidly, and this effect predominates over the greater cell density. FIG. 2B shows the ratio of area to gate width (A/W) as a function of Y.sub.SB, which is the surface dimension of the opening or "doughnut hole" in the polysilicon gate (see FIG. 1A). A/W is a geometrical figure of merit, since it is desirable to minimize the area required to provide a given amount of gate width. A/W falls as Y.sub.SB increases until Y.sub.SB =Y.sub.gate, at which A/W begins to rise with increasing Y.sub.SB. The two curves in FIG. 2B are for Y.sub.gate =5 .mu.m and Y.sub.gate =2 .mu.m.
FIGS. 2C and 2D are graphs showing the normalized on-resistance R.sub.DS A as a function of the gate length Y.sub.gate and cell density, respectively. In both cases the on-resistance falls to a minimum after which it begins to rise. In the case of FIG. 2C the rise is primarily the result of current-crowding in the JFET area; in FIG. 2D, the rise is a function of geometry (i.e., the total channel width decreases after the cell density passes the point where Y.sub.gate =Y.sub.SB. The curves in each graph are for Y.sub.gate =5 .mu.m and Y.sub.gate =2 .mu.m, respectively.
The net effect of FIGS. 2A-2D is that reductions of the on-resistance of a vertical DMOSFET are subject to certain limitations based on cell geometry and current-pinching in the JFET region of the device. The latter is illustrated in FIG. 3A, which is a simulated cross-sectional view of the current in a vertical DMOSFET having a given gate length, and in FIG. 3B, which is a similar view showing the current-crowding which occurs as the gate length is reduced. FIG. 3C is a graph showing the voltage at the cross-section at the center of the MOSFET cell as a function of the distance X below the surface of the silicon. Curve A shows the voltage at the cross-section AA in FIG. 3A and curve B shows the voltage at the cross-section BB in FIG. 3B. In FIG. 3B the voltage rises rapidly just below the silicon surface as a result of current-pinching, and then it rises more gradually as a result of the IR drop in the epitaxial drain. When the gate is wider as in FIG. 3A the voltage rises gradually from the silicon surface. There is no sharp voltage jump below the silicon surface as a result of current-crowding. Despite the lower voltage drop across the JFET pinch region, the magnitude of the voltage drop across the entire device may or may not be larger depending on the magnitude of the channel resistance. FIG. 3C illustrates the equivalent lumped element circuit of the vertical planar DMOSFET in its linear "switch" operating condition. Conduction in the JFET region is actually somewhat complex, since the current spreads laterally before turning to flow vertically through the JFET pinch region.
What is needed is a way to reduce the JFET resistance (i.e., the resistance in the JFET pinch region) and the total resistance of a low voltage MOSFET without adversely affecting the breakdown voltage of the device.